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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 79

LHLL

LLPL

PLSCL

SCLSCH

PLPH

AVLL

AVIV

LLAX

AZPL

LLIV

PLIV

PXIX

SCXIX

PXIZ

SCXIZ

A8-A15

A0-A7 Instr. In A0-A7

A8-A15

ALE

XCSCODE

XPSEN

Figure 9.6-12:

Code Read Cycle

Symbol Parameters Min Max Unit

RLRH

XRD pulse width

12T − 0.7

WLWH

XWR pulse width

12T − 0.8

LLAX2

Address hold after ALE 4T + 1.9 ns

RLDV

XRD to valid data in

10T − 33.9

RHDX

Data hold after XRD 0 ns

RHDZ

Data float after XRD 4T + 1.1 ns

LLDV

ALE low to valid data in

16T − 31.7

AVDV

Address to valid data in

18T − 41.7

LLWL

ALE to XWR or XRD 6T + 1.0 6T + 2.5 ns

AVWL

Address valid to XWR or XRD

8T − 7.3

WHLH

XWR or XRD high to ALE high

2T − 2.0 2T − 0.,8

QVWX

Data valid to XWR↓ 2T − 6.5

QVWH

Data setup to XWR

14T − 7.3

WHQX

Data hold after XWR 2T + 1.7 ns

RLAZ

Address float after XRD 0 ns

AVSDL

Address valid to XCSDATA 12.6 ns

SDLSDH

XCSDATA pulse width

24T − 5.0

for Port A = 120pF; C

for XPSEN = 10pF; C

for all others = 80pF)

Table 9.6-11:

Timing Values for Accesses to the Data Memory

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 93 94

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