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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 77

No. Parameters Min Max Unit

Address setup time to AS ↓

0ns

AS ↓ to Data valid (access to RAM)

4T + 27 ns

AS ↓ to Data valid (access to the registers)

4T + 27 ns

Address (AB

12..0

) hold time after AS ↑

10 ns

R_W ↓ setup time to AS ↓

10 ns

64 AS Pulse Width

6T − 10

Data hold time after AS ↑

38ns

66 AS inactive time 10 ns

R_W hold time after AS ↑

10 ns

XCS ↓ setup time to AS ↓

-5 ns

XCS hold time after AS ↑

0ns

AS ↓ to XDSACK ↓ (standard Ready)

5T + 25 ns

AS ↓ to XDSACK ↓ (early Ready)

4T + 25 ns

XDSACK hold time after AS ↑

425ns

73 AS cycle time 6T ns

Data setup time to AS ↑

10 ns

Data hold time after AS ↑

10 ns

76 AS Pulse Width 4T ns

last AS ↓ (Read) to XCS ↓

4T+10 ns

XCS ↑ to next AS ↑ (Write)

4T ns

79 AS to next AS (Write, XCS don’t care) 6T ns

Table 9.6-9: Timing Values for the Asynchronous Motorola Mode

VALID

Data Out

AB(12..0)

DB(7..0)

R_W

E_Clock = log.'0'

XDSACK

(normal)

XDSACK

(early)

XCS

6877

Figure 9.6-10: Asynchronous Motorola Mode, Processor Read Timing

1 2 ... 74 75 76 77 78 79 80 81 82 83 84 ... 93 94

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