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DPC31 HW

Page 14 Version V 1.0

DPC31 HW Description

0000h Int-Req-Reg

7..0

Interrupt Controller Register

0001h Int-Req-Reg

15..8

0002h Int-Req-Reg

23..16

0003h Int-Req-Reg

28..24

0004h Int-Ack-Reg

7..0

0005h Int-Ack-Reg

15..8

0006h Int-Ack-Reg

23..16

0007h Int-Ack-Reg

28..24

0008h Int-Mask-Reg

7..0

0009h Int-Mask-Reg

15..8

000Ah Int-Mask-Reg

23..16

000Bh Int-Mask-Reg

28..24

000Ch Int-EOI-Reg

000Dh

000Eh reserved

000Fh

0010h C31_Ctrl-Reg

6..0

Refer to Chapter 6

0011h Mode-Reg1-Set

7..0

Refer to Chapter 6

0012h Mode-Reg1-Reset

7..0

Refer to Chapter 6

0013h User_InstQ_Write-Cmd

7..0

Transfers a new request to the sequential control system

0014h

... reserved

001Fh

0020h SSC_Transmit-Buf

7..0

Receive buffer of the SSC interface

0021h SSC_Sts-Reg

7..0

Status register of the SSC interface

0022h SSC_Ctrl1-Reg

7..0

Control register of the SSC interface

0023h SSC_Ctrl2-Reg

2..0

Control register of the SSC interface

0024h SSC_Int_Enable-Reg

3..0

Interrupt_Enable register of the SSC interface

0025h SSC_Baudrate-Reg

7..0

Baudrate register of the SSC interface

0026h

... reserved

07FFh

Table 3.2-1:

Assignment of the Internal Register Cells for WRITE

3.3 Organizational Parameters (RAM)

The organizational parameters are stored by the user in the RAM under the addresses specified in the table

below. These parameters primarily describe the parameter cells and the buffer pointers of the

communication profile (buffer management).

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 93 94

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