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DPC31 HW
SchnittStellenCenter
DPC31 HW Description
Version V1.0 Page 21
Copyright (C) Siemens AG 2000. All rights reserved. 12/00
5 Communication Functions of the Sequential Control System
PROFIBUS Layer2 and the DP slave module are implemented in the sequential control system. Layer2 is
composed of a MAC (media access control) part and an FLC (interface services) part. In the following, the
Layer2 module is simply called MAC module. The user can influence only the cells that are described here.
5.1 Setting Up the DP Buffer Structures
To set up the DP buffers, the corresponding buffer pointers are entered in the organizational parameters and
the buffers lengths are entered in the buffers. All pointers are 8-Bit segment buffer pointers. During access,
the sequential control system adds an 8-Bit offset address to the segment address that has been shifted by
5-Bits (x32) (result: 13-Bit physical address). Therefore, the list and buffer start addresses, have a
granularity of 32 bytes.
5.1.1 Structure of the Buffers
Figure 5.1-1 shows the structure of the request buffers and response buffers for the DPS SAPs
SAP Buffers
Header Field: Reserved
Length_Data_Buffer
Reserved
Reserved
Reserved
Reserved
Data Field: Data 0
Data 1
.....
Data 243
Figure 5.1-1:
Structure of the SAP Buffers
Length_Data_Buffer:
This value specifies the length of the data field in the request buffer. If the net data length of the
request message is larger than the available buffer length, the MAC responds with “No Resource’.
Except for the DIN and Dout buffers, the user must enter the length in all buffers!
5.1.2 Request Interface for DPS (Instruction Queue)
User requests to the DPS module are transferred via a request interface. This request list is a polling list
onto which the user transfers communication requests. Figure 5.1-2 shows the organization of the
Instruction_Queue. With each entry (5 bytes respectively), the user must also transfer the command to the
sequential control system. This is done with a write operation with any data value to the register cell
‘User_InstQ_Write Cmd’. The organization of the Instruction_Queue includes the following parameters:
InstQ_Base Ptr: The Instruction_Queue segment pointer
InstQ_Length: Describes the length of the Instruction_Queue and is a multiple of the length of an
entry (n*5)
InstQRd Ptr: An Offset_Pointer which points to the next entry that is to be read (and is managed
by the DPC31)
InstQ_Wr Ptr: An Offset_Pointer which points to the next free entry (and is managed by the user)
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