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DPC31 HW
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DPC31 HW Description
12/00 Copyright (C) Siemens AG 2000. All rights reserved.
IRR IMR FF
IAR
Host
IRR
Write
IRR
Read
IAR
IRR
EOI
INT-Pol
INT
PG
5
IRR IMR FF
IAR
C31 Core
IRR
Write
IRR
Read
IAR
IRR
EOI
INT
PD
2/
XINT0
Profibus
Sequencer
DPC31
Figure 7.1-6:
Interrupt Controller of the µP Interface and C31 Core in the DPC31
The polarity of the interrupt input can be parameterized (Mode Register1; refer to Chapter 3.3: INT_Pol).
After the HW reset, the output is low-active.
Interrupt Request Register, IRR (writable, readable):
New_GC_
Command
Go/Leave_
Data_
Exchange
IndQ_Full IndQ_Entry 0 0 Diag_
Fetched
WD_State_
Changed
7 0
DX_OUT_
Overflow
DX_OUT Diag_
Buffer_
Changed
Get_Cfg_
Buffer_
Changed
New_Cfg_
Data
0 New_Prm_
Data
New_SSA
_Data
15 8
00000000
23 16
00000SSC_
Interface
RAM_
Access_
Violation
0
28
24
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