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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 69

9.5.3 DC Specification of the Pad Cells

Parameters Name Condition Min. Typ. Max. Unit

Input Voltage 0-Level V

00.8V

Input Voltage 1-Level V

2.0 5.5 V

Output Voltage 0-Level V

= 0 mA 0.1 V

Output Voltage 1-Level V

= 0 mA

− 0.2

Schmitt Trig. +ve threshhold V

1.2 2.4 V

Schmitt Trig. -ve threshold V

0.6 1.8 V

Schmitt Trig. Hysteresis V

0.3 1.5 V

Input Leakage Current I

= V

or GND

±10

-5

±10

µA

Output Current 0-Level

3 mA cell / 5V tolerant

= 0.4 V 3 mA

Output Current 1-Level

3 mA cell / 5V tolerant

= 2.4 V

−2

Output Current 0-Level

9 mA cell / 5V tolerant

= 0.4 V 9 mA

Output Current 1-Level

9 mA cell / 5V tolerant

= 2.4 V

−2

Output Current 0-Level

9 mA cell / 3.3V

= 0.4 V 9 mA

Output Current 1-Level

9 mA cell / 3.3V

= 2.4 V

−9

Tristate Output Leakage

Current

= V

or GND

±10

µA

Short Circuit Current I

= 0 V

−250

Input Capacity C

@ f = 1 MHz 10 20 pF

Output Capacity C

OUT

@ f = 1 MHz 10 20 pF

I/O Capacity C

I/O

@ f = 1 MHz 10 20 pF

Table 9.5-1:

DC Specification of the Pad Cells

9.6 AC Specification

9.6.1 Driver Capability

The run times at the chip outputs always depend on the driver capacity of the pad cells as well as on the

assumed capacitive load. The capacitive load that was used as a basis for the following timing specifications

is shown in Table 9.6-1. To specify the maximum and minimum runtimes, the variations of temperature

range and supply voltage range shown in Table 9.3-1 were included also.

1 2 ... 66 67 68 69 70 71 72 73 74 75 76 ... 93 94

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Siemens SPC3 Specifiche Pagina 71

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