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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 45

Description of the SSC Module:

The SSC module consists of a transmit channel and a receive channel. Each channel contains a 9-bit shift

The user operates the transmit buffer. If the transmit buffer is empty, the transmitter generates the Transmit

Buffer Empty which can be polled via the status register, or which, with a corresponding enable in the

Interrupt Enable Register, activates the SSC interrupt. After loading the transmit buffer, Transmit Buffer

Empty enters inactive. As soon as the transmit shift register is free, the data byte is transferred there and

shifted out. The clock (SSCLK) is generated only as long as the shift process is running. During continuous

sending, the user always writes the next data byte to the transmit buffer while one is being shifted out.

In the receiver, the arriving bits are shifted to the Receiver Shift Register. After 8 data bits have been

received, or 9 bits with enabled parity, this data byte is accepted in the receive buffer and Receive Buffer Full

is generated. This state can be polled via the status register or it can be activated as SSC _Interface

interrupt if there is a corresponding enable in the Interrupt Enable Register.

If there is continuous receiving, the user reads a data byte from the receive buffer while the next one is

arriving at the receiver shift register. Error states (Receive Buffer Overflow, RECERR; or Parity Error, PERR)

can be polled in the status register or can be generated as SSC_Interface interrupt (enable in the Interrupt

Enable Register).

Because of the full duplex channel in the SSC module, it can receive while it is sending. However, the

protocols process only half-duplex (SPI E²PROM, etc.). For that reason, the received data is to be ignored

(disable the corresponding interrupts). The last received data byte is always in the receive buffer. To receive

user data, dummy data bytes have to be sent so that the SSC module generates a clock pulse.

The user (external µP or C31) addresses the SSC module in the address range from 0020h to 0025h. It can

be polled or operated with interrupt output. The interrupt runs to the two interrupt controllers (refer to Chapter

7.1.4).

Control1 Register:

Bit Position76543210

BREN - PODD PPOS PEN HCB CPOL CPHA

Default 00000011

rw r rwrwrwrwrwrw

CPHA: Clock Phase Control Bit

=0 Acceptance of the receive data at the leading clock edge; sending at the back

clock edge.

=1 Shifting the send data at the leading clock edge; receiving at the back clock edge.

CPOL: Clock Polarity Control Bit

=0 Clock idle state is ‘low’; leading clock edge is a low-to-high edge.

=1 Clock idle state is ‘high’; leading clock edge is high-to-low edge.

HCB: Heading Control Bit

=0 Send/receive LSB first.

=1 Send/receive MSB first.

PEN: Parity Control Bit

=0 Generating/checking parity disabled.

=1 Generating/checking parity enabled.

PPOS: Parity Position Control Bit

=0 Send/receive parity bit last.

=1 Send/receive parity bit first.

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 93 94

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