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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 5

7 DESCRIPTION OF THE HARDWARE BLOCKS 35

7.1 Universal Processor Interface 35

7.1.1 Bus Interface Unit (BIU) 35

7.1.2 IO Interface 40

7.1.3 Interface Signals 41

7.1.4 Interrupt Controller of the µP Interface in the DPC31 41

7.2 Synchronous Serial Interface (SSC Interface) 44

7.3 80C31 Core and Interface 48

7.3.1 Reset Phase of the C31 48

7.3.2 80C31 Core and Internal Memory 49

7.3.3 Expansion Interface to the 80C31 Core 51

7.3.4 Interface Signals 51

7.4 C31 Interrupt Controller in the DPC31 52

7.5 Serial PROFIBUS Interface 52

7.5.1 Asynchronous Physics Unit (NRZ) 52

7.5.2 Synchronous Physics Unit (Manchester) 53

7.6 DPS Watchdog Timer 61

7.7 Watchdog Timer 61

7.7.1 Automatic Baudrate Detection 61

7.7.2 Baudrate Monitoring 61

7.7.3 Response Monitoring 62

7.8 Clock Supply 62

7.8.1 PLL 62

8 TEST SUPPORT 64

8.1 Emulator Connection for the C31 64

9 ELECTRICAL SPECIFICATIONS 65

9.1 Maximum Limits 66

9.2 Permitted Operating Values 66

9.3 Guaranteed Operating Range for the Specified Parameters 66

9.4 Power Loss 66

9.5 Pad Cells 67

9.5.1 Power-Up of the Supply Voltage 67

9.5.2 Structure of the Pad Cells with 5V Tolerance 67

9.5.3 DC Specification of the Pad Cells 69

9.6 AC Specification 69

9.6.1 Driver Capability 69

9.6.2 Timing Diagrams, Signal Run Times 70

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Siemens SPC3 Specifiche Pagina 7