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DPC31 HW

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DPC31 HW Description

Version V1.0 Page 51

7.3.3 Expansion Interface to the 80C31 Core

Via the ports A, B, C, and D, the ALE and XPSEN signal, all signals of the C31 are taken outside. The C31

must always be operated with address and data bus because the internal memory of the DPC31 is connected

to it. The exact assignment is provided in Table 7.3-2 (function/alternative function). PD

is not to be used;

here, the interrupt of the sequential control system is located that is always taken permanently to the outside.

In addition, the following signals are generated: “XCSDATA” (chip select external data memory (RAM)) and

“XCSCODE” (chip select external program memory (ROM)). XCSDATA = low if the access is made to the

external data area (starting with address 2000h). XSCODE = low, if the external code area is accessed (for

Boot Type 2, continuous). These signals are always to be connected so that there will not be driver conflicts

when connecting an In Circuit Emulator (ICE).

This makes connecting a standard In Circuit Emulator for an 8052 controller (24 MHz) possible. For this, the

pin has to be wired DBX = high.

7.3.4 Interface Signals

Pin Name Function Alternative Fct. DebugMode (ICE)

DBX = '1'

Comment

Type Signal

Name

Type Signal

Name

Type Signal

Name

Type

7..0

I/O AB

7..0

I/O - AB

7..0

I/O Multiplexed address/data bus

I/O P1.0 I/O T2 I - I

I/O P1.1 I/O T2EX I - I

2..7

I/O P1.2 ...

P1.7

I/O - - I

7..0

I/O AB

15..8

O- AB

15..8

I Address bus more significant

byte

I/O P3.0 I/O RXD I - I

I/O P3.1 I/O TXD O - I

I/O XINT0 O - XINT0 O Interrupt of the seq. ctrl. syst.

I/O P3.3 I/O XINT1 I - I Ext. interrupt

I/O P3.4 I/O T0 I I

I/O P3.5 I/O T1 I I

I/O XWR O - XWR I

I/O XRD O - XRD I

ALE I/O ALE O - ALE I Address Latch Enable

XPSEN I/O XPSEN O - XPSEN I Output Enable for Code-

Memory

XCSDATA O XCSDATA O - XCSDATA O Chip Select for Data Memory

XCSCODE O XCSCODE O - XCSCODE O Chip Select for Code Memory

DBX I DBX I - DBX I In Circuit Emulator debug mode

Table 7.3-2:

Interface Signals of the C31

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 93 94

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